Job opportunity
Senior RTL Design Engineer - Verilog & SoC Architect
Lancesoft
Lancesoft is seeking an experienced RTL Design Engineer in Canada to design and verify RTL blocks using Verilog HDL for chip implementation. The role requires strong SoC architectural understanding and the ability to specify microarchitectures for new and modified functions.
The candidate will perform linting and simulation, collaborating with synthesis and backend teams to drive physical implementation. A senior profile with 10 years of experience is expected.
#J-18808-Ljbffr
Apply on source site The candidate will perform linting and simulation, collaborating with synthesis and backend teams to drive physical implementation. A senior profile with 10 years of experience is expected.
#J-18808-Ljbffr