Job opportunity
PCIe DV Engineer - SV/UVM (Gen3-5)
HCL Technologies Limited
HCL Technologies Limited is seeking a Design Verification Engineer to join our semiconductor verification team in Canada. You will design and develop robust SV/UVM-based verification environments, verify PCIe Gen3/Gen4/Gen5 protocols, and contribute to reusable testbenches and methodologies.
You should be proficient in SVA, coverage-driven verification, and constrained-random testing, with experience using simulators such as VCS, Xcelium, or Questa.
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Apply on source site You should be proficient in SVA, coverage-driven verification, and constrained-random testing, with experience using simulators such as VCS, Xcelium, or Questa.
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