Logic Equivalence Checking Engineer

Develop formal equivalence methodologies for complex SoC designs using Cadence Conformal, Synopsys Formality, and automation scripting.
As a LEC CAD Engineer, you will support functional correctness across RTL, synthesized netlists, and physical designs. You will own sign-off methodologies, enable ECO flows, debug non-equivalences, and optimize verification tools. Your work spans RTL-to-GDS and gate-to-gate flows.
Key Responsibilities:

Own end-to-end LEC sign-off methodologies across design flows
Enable ECO flows for safe late-stage design modifications
Debug non-equivalences, aborts, and mismatches across stages
Maintain Tcl, Python, Perl, or Shell automation
Optimize verification tool runtime, capacity, and scalability
Requirements:

Proficiency with Cadence Conformal LEC and ECO tools
Proficiency with Synopsys Formality
Bachelor's or Master's degree in Electrical Engineering
Degree in Computer Science or related field
Dedicated hardware or EDA experience
Apply formal verification, ECO, debugging, and automation expertise to support functional correctness throughout complex SoC development.

#J-18808-Ljbffr