Job opportunity
Senior ASIC Physical Design Lead for SoC Tapeouts
Qualcomm
Qualcomm Canada ULC is seeking a senior ASIC Physical Design engineer to lead end‑to‑end PD flows for SoCs and retimers. You will collaborate with front‑end, analog/SerDes, DFT, and packaging teams to drive tapeouts and ensure design convergence.
The role requires strong experience with CTS, DRC/LVS, and access to Cadence Innovus or Synopsys ICC2, plus scripting in Python or Tcl to automate flows.
#J-18808-Ljbffr
Apply on source site The role requires strong experience with CTS, DRC/LVS, and access to Cadence Innovus or Synopsys ICC2, plus scripting in Python or Tcl to automate flows.
#J-18808-Ljbffr