Job opportunity
Senior ASIC RTL Architect for High-Performance IP
European Recruitment BV
European Recruitment BV is seeking experienced Verification engineers in Ottawa to work on leading-edge ASIC projects for North American clients. You will translate architectural requirements into synthesizable SystemVerilog/Verilog, owning blocks from spec through front-end sign-off, with a focus on power, performance and physical implementation.
You will collaborate with architecture, RTL, firmware, DV, and PD teams to deliver complex, high-performance silicon and meet project milestones with
#J-18808-Ljbffr
Apply on source site You will collaborate with architecture, RTL, firmware, DV, and PD teams to deliver complex, high-performance silicon and meet project milestones with
#J-18808-Ljbffr