Job opportunity
Physical Design Engineering Director Toronto
Astera Labs
Lead physical design for high-speed connectivity ASICs as Astera Labs’ Physical Design Engineering Director, fully on-site in Toronto.
You will guide implementation from RTL to GDSII for PCIe retimers, Ethernet retimers, and signal conditioning solutions. The role combines hands-on technical leadership with people management across floorplanning, place-and-route, timing closure, and sign-off. You will build the Toronto physical design team for the Signal Connectivity Group.
Key Responsibilities:
Lead physical design execution from floorplan through tapeout
Drive synthesis, place-and-route, CTS, extraction, and timing closure
Coordinate design convergence with RTL, DFT, STA, EMIR, and verification
Mentor engineers, hire team members, and plan sprints
Coordinate methodology with global physical design teams
Requirements:
Bachelor’s degree in electrical or computer engineering
15+ years implementing complex SoCs at 7nm or below
5+ years leading teams or projects
Experience with Cadence Innovus or Synopsys Fusion Compiler or ICC2
Scripting ability in Tcl, Python, or Perl
Bring physical design leadership, advanced-node implementation, and team-building expertise to Astera Labs’ Toronto connectivity programs.
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Apply on source site You will guide implementation from RTL to GDSII for PCIe retimers, Ethernet retimers, and signal conditioning solutions. The role combines hands-on technical leadership with people management across floorplanning, place-and-route, timing closure, and sign-off. You will build the Toronto physical design team for the Signal Connectivity Group.
Key Responsibilities:
Lead physical design execution from floorplan through tapeout
Drive synthesis, place-and-route, CTS, extraction, and timing closure
Coordinate design convergence with RTL, DFT, STA, EMIR, and verification
Mentor engineers, hire team members, and plan sprints
Coordinate methodology with global physical design teams
Requirements:
Bachelor’s degree in electrical or computer engineering
15+ years implementing complex SoCs at 7nm or below
5+ years leading teams or projects
Experience with Cadence Innovus or Synopsys Fusion Compiler or ICC2
Scripting ability in Tcl, Python, or Perl
Bring physical design leadership, advanced-node implementation, and team-building expertise to Astera Labs’ Toronto connectivity programs.
#J-18808-Ljbffr