Job opportunity
Senior Analog Layout Engineer — 3nm/5nm SoCs
leadIC Design Pvt Ltd
leadIC Design Pvt Ltd in Ottawa, Canada is seeking an experienced Analog Layout Engineer to join our on-site team. You will work on advanced SoCs and IPs, delivering full custom layouts for analog and mixed-signal blocks using Cadence Virtuoso on TSMC 3nm/5nm processes.
The role requires 5+ years in analog/mixed-signal layout, strong extraction and PEX skills, and collaboration with circuit designers across multiple corners to meet tight area, power, and performance targets.
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Apply on source site The role requires 5+ years in analog/mixed-signal layout, strong extraction and PEX skills, and collaboration with circuit designers across multiple corners to meet tight area, power, and performance targets.
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